The present invention relates to a bit synchronization method and circuit that receives digital data synchronized with a first clock signal, and outputs the data in synchronization with a second clock signal that is not synchronized with the first clock signal, the second clock signal having a higher frequency then the first clock signal.
The purpose of a bit synchronization circuit is to synchronize and reshape the incoming signal, and to prevent bit slip by absorbing clock jitter and frequency error. Bit slip refers to the skipping of a bit, or output of the same bit twice. Bit synchronization is particularly necessary in equipment that must process high-speed digital signals, including, for example, various equipment used in broadband integrated services digital networks (B-ISDN equipment). The present invention is useful in, for example, carrier equipment, multiplexing equipment, switching equipment, and in general any equipment that receives digital signals in which the bits are not synchronized with a clock signal employed in the equipment.
The present invention is an improved version of the elastic store method. In the elastic store method, the incoming data signal is routed through a parallel bank of flip-flop circuits (flip-flops). The flip-flops are selected cyclically for both writing input data and reading output data. The write cycle is controlled by the first clock signal. The read cycle is controlled by the second clock signal.
The read and write cycles must be kept out of phase with each other, to avoid access conflicts. If an access conflict occurs (if a flip-flop is written to while being read), the conventional elastic store method takes corrective action by adjusting the phase of the write cycle. Since the write-cycle phase must be synchronized with the first clock signal, in adjusting the phase, the conventional method cannot make use of the higher frequency of the second clock signal. The conventional method has several disadvantages.
One disadvantage is that every adjustment of the phase of the write cycle is accompanied by bit slip.
Another disadvantage is that, depending on the amount of mutual jitter between the first and second clock signals, an excessive number of flip-flops may be needed to reduce the probability of bit slip to an acceptably low level. The attendant large size of the bit synchronization circuit can present problems, particularly in a device that receives many data signals and requires a separate bit synchronization circuit for each signal, or a device that receives a parallel data signal and requires a separate set of flip-flops for each parallel bit of data.
Yet another disadvantage is that, no matter how many flip-flops are provided, bit slip will occur periodically unless the frequency of the second clock signal is an exact integer multiple of the frequency of the first clock signal. In many cases the first and second clock signals are generated by different oscillators, making an exact frequency relationship difficult to maintain.